1. Field of the Invention
The present invention relates to a Static Random Access Memory (to be simply referred to as an SRAM hereinafter) and, more particularly, to the structure and layout of a memory cell as a semiconductor element.
2. Description of the Prior Art
In general, an SRAM using flip-flops as data storage means is faster than a Dynamic Random Access Memory (to be referred to as a DRAM hereinafter) using capacitors as data storage means, and requires no data refresh. On the other hand, the number of elements constituting one memory cell of the SRAM is larger than that of the DRAM, and hence the area of one memory cell of the SRAM is several times larger than that of the DRAM.
As shown in FIG. 6, a conventional, basic CMOS (Complementary Metal Oxide Semiconductor) SRAM cell circuit includes two PMOS transistors 301 and 302 and four NMOS transistors 311, 312, 321, and 322.
The source terminals of the two PMOS transistors 301 and 302 are respectively connected to power supply (Vdd) lines. The source terminals of the two NMOS transistors 311 and 312 are respectively connected to ground (Gnd) lines. The drain terminal of the PMOS transistor 301 is connected to the drain terminal of the NMOS transistor 311. The gate terminal of the PMOS transistor 301 is connected to the gate terminal of the NMOS transistor 311. Similarly, the drain terminal of the PMOS transistor 302 is connected to the drain terminal of the NMOS transistor 312. The gate terminal of the PMOS transistor 302 is connected to the gate terminal of the NMOS transistor 312. As is obvious from this arrangement, the PMOS transistor 301 and the NMOS transistor 311 constitute a CMOS inverter. Similarly, the PMOS transistor 302 and the NMOS transistor 312 constitute a CMOS inverter. One input terminal of each of the two CMOS inverters is connected to the other output terminal thereof so as to constitute a flip-flop.
One of the source and drain terminals of each of the NMOS transistors 321 and 322 is connected to one output terminal of a corresponding one of the two CMOS inverters, and the other of the source and drain terminals of each transistor is connected to a corresponding one of two bit lines D and DB. The gate terminals of the two NMOS transistors are connected to a word line WL. The NMOS transistors 321 and 322 are connected in this manner to serve as transfer gates between the flip-flop and the bit lines. Note that an inverted signal of a signal input to the bit line D is input to the bit line DB.
The operation of the CMOS SRAM cell circuit having the above arrangement will be described below. When the potential of the word line WL is set at High level, the two NMOS transistors 321 and 322 serving as the transfer gates are tuned on. As a result, data is written in the flip-flop or read out therefrom in accordance with complementary signals transferred through the bit lines D and DB. In contrast to this, when the potential of the word line WL is set at Low level, the two NMOS transistors 321 and 322 serving as the transfer gates are turned off, the data written in the flip-flop immediately before the transistors are turned off is held.
The structure of a CMOS SRAM cell circuit (to be referred to as reference 1), of the above CMOS SRAM cell circuits, which is formed on a silicon substrate by using a bulk CMOS technique will be described next with reference to FIGS. 1 and 2. As shown in FIG. 1, the CMOS SRAM cell circuit as reference 1 includes element regions 910, 920, and 930, gate interconnections, 941, 942, and 943, first aluminum interconnections 952, 971, and 972, second aluminum interconnections 951, 961, and 962, contact holes 980a to 980j, and through holes 990a to 990c. In this case, the term "element region" is a general term indicating a region, on the silicon substrate, on which the source diffusion layer, drain diffusion layer, and channel region of a MOS transistor are formed. In addition, the gate interconnection 941 corresponds to the word line WL in FIG. 6, and the second aluminum interconnections 961 and 962 respectively correspond to the bit lines D and DB in FIG. 6. The second aluminum interconnection 951 and the first aluminum interconnection 952 are ground potential (Gnd) lines and electrically connected to n.sup.+ -type diffusion layer regions 911 and 921 (see FIG. 2) serving as the sources of NMOS transistors (NMOS transistors 311 and 312 in FIG. 6) constituting a flip-flop through the through hole 990a and the contact holes 980a and 980b. Although not shown, a power supply voltage (Vdd) is applied to a p.sup.+ -type diffusion layer region 931 in the element region 930.
FIG. 2 is a plan view showing only the element regions 910, 920, and 930 and the gate interconnections 941, 942, and 943 of the cell structure shown in FIG. 1. N.sup.+ -type diffusion layer regions 911, 912, 913, 921, 922, and 923 of NMOS transistors (corresponding to the NMOS transistors 311, 312, 321, and 322 in FIG. 6) using the gate interconnections 942 and 943 and the gate interconnection 941 corresponding to the word line WL as gates are formed in the element regions 910 and 920. P.sup.+ -type diffusion layer regions 931, 932, and 933 of PMOS transistors (corresponding to the PMOS transistors 301 and 302 in FIG. 6) using the gate interconnections 942 and 943 as gates are formed in the element region 930.
More specifically, the constituent elements shown in the plan view of FIG. 2 respectively correspond to the elements of the circuit in FIG. 6 as follows. Of the MOS transistors each using the gate interconnection 942 as a gate in FIG. 2, the PMOS transistor having the p.sup.+ -type diffusion layer regions 931 and 932 as a source and a drain, respectively, corresponds to the PMOS transistor 301 in FIG. 6. The NMOS transistor having the n.sup.+ -type diffusion layer regions 911 and 912 as a source and a drain, respectively, corresponds to the NMOS transistor 311 in FIG. 6. Similarly, of the MOS transistors each using the gate interconnection 943 as a gate in FIG. 2, the PMOS transistor having the p.sup.+ -type diffusion layer regions 931 and 933 as a source and a drain, respectively, corresponds to the PMOS transistor 302 in FIG. 6. The NMOS transistor having the n.sup.+ -type diffusion layer regions 921 and 922 as a source and a drain, respectively, corresponds to the NMOS transistor 312 in FIG. 6. Of the MOS transistors using the gate interconnection 941 as a gate, the NMOS transistor having the n.sup.+ -type diffusion layer regions 912 and 913 as a source and a drain, and vice versa, respectively, corresponds to the NMOS transistor 321 in FIG. 6. The NMOS transistor having the n.sup.+ -type diffusion layer regions 922 and 923 as a source and a drain, and vice versa, respectively, corresponds to the NMOS transistor 322 in FIG. 6.
Referring to FIG. 1 again, the second aluminum interconnection 951 is a ground potential (Gnd) line and connected to the first aluminum interconnection 952 through the through hole 990a. The first aluminum interconnection 952 is connected to the n.sup.+ -type diffusion layer regions 911 and 921 (see FIG. 2) through the contact holes 980a and 980b. With this arrangement, the Gnd potential is applied to the n.sup.+ -type diffusion layer regions 911 and 921. Although not shown, the power supply potential Vdd is applied to the p.sup.+ -type diffusion layer region 931, as described above. Referring to FIGS. 1 and 2, the p.sup.+ -type diffusion layer region 932 and the n.sup.+ -type diffusion layer region 912 are connected to the first aluminum interconnection 971 through the contact holes 980c and 980d. The first aluminum interconnection 971 is connected to the gate interconnection 943 through the contact hole 980e. The p.sup.+ -type diffusion layer region 933 and the n.sup.+ -type diffusion layer region 922 are connected to the first aluminum interconnection 972 through the contact holes 980f and 980g. The first aluminum interconnection 972 is connected to the gate interconnection 942 through the contact hole 980h. With the above connection, the flip-flop in FIG. 6 is formed.
The second aluminum interconnections 961 and 962 in FIG. 1 respectively correspond to the bit lines D and DB in FIG. 6. The gate interconnection 941 in FIG. 1 corresponds to the word line WL in FIG. 6. The n.sup.+ -type diffusion layer regions 913 and 923 in FIG. 2 are respectively connected to the second aluminum interconnections 961 and 962 serving as the bit lines D and DB through the through holes 990b and 990c. With this connection, since the gate interconnection 941 serves as the gate of the NMOS transistors 321 and 322 in FIG. 6, transfer gates which are turned on/off in accordance with signals transferred through the word line WL are formed between the bit lines D and DB and the internal terminals of the flip-flop.
The cross-sectional structure of the CMOS SRAM cell as reference 1 will be described next with reference to FIG. 3. FIG. 3 shows the cross-section designated in FIG. 2.
As shown in FIG. 3, in the CMOS SRAM cell as reference 1 using the bulk CMOS technique, a p-type well region 1051 and an n-type well region 1052 are formed in a silicon substrate 1060. NMOS transistors each using the gate interconnection 942 as a gate are formed in the element region in the p-type well region 1051. PMOS transistors each using the gate interconnection 942 as a gate are formed in the element region in the n-type well region 1052. An oxide film 1070 for element isolation is formed between the NMOS transistors and the PMOS transistors. The Gnd potential is applied to the p-type well region 1051, and the Vdd potential is applied to the n-type well region 1052 to reversely bias the p-n junction portion between the p-type well region 1051 and the n-type well region 1052, thereby realizing element isolation. To apply these two element isolation techniques to this structure, a space of several pm or more must be ensured between the n.sup.+ -type diffusion layer region 912 and the end portion, of the n-type well region 1052, which is close to the p-type well region 1051 and between the p.sup.+ -type diffusion layer region 932 and the end portion, of the p-type well region 1051, which is close to the n-type well region 1052. For example, in a CMOS process based on a 0.35-.mu.m rule, an element isolation space of 2 to 3 .mu.m or more must be ensured between the p.sup.+ -type diffusion layer region 932 and the n.sup.+ -type diffusion layer region 912. That is, this element isolation space is one of the factors which interfere with a reduction in area of an SRAM cell.
The SOI (Silicon On Insulator) CMOS technique has recently attracted considerable attention as a method of solving the problem posed in the bulk CMOS technique like reference 1. According to the SOI CMOS technique, MOS transistors, diffusion layer regions, and the like are formed on an insulating film and isolated from each other by the insulating film. For this reason, unlike the above bulk CMOS technique, no well structure is required to isolate an n.sup.+ -type diffusion layer region from a p.sup.+ -type diffusion layer region. Therefore, when the same potential is to be applied to the n.sup.+ -type diffusion layer region and the p.sup.+ -type diffusion layer region, the two regions are formed to be adjacent to each other without being isolated. In addition, when different potentials are to be applied to these diffusion layer regions, the space between the regions can be reduced to the minimum space defined by process conditions.
For example, such an SOI CMOS technique is applied to the CMOS SRAM cell (to be referred to as reference 2 hereinafter) disclosed in Japanese Unexamined Patent Publication No. 62-81055. The CMOS SRAM cell as reference 2 has an SRAM structure in which an n.sup.+ -type diffusion layer region having NMOS transistors and a p.sup.+ -type diffusion layer region having PMOS transistors, to which regions the same potential is to be applied, are formed to be adjacent to each other without being isolated by a field oxide film or the like, and are directly connected to each other without using any aluminum interconnection. The CMOS SRAM cell as reference 2 is characterized in that, for example, the n.sup.+ -type diffusion layer region 912 and the p.sup.+ -type diffusion layer region 932 in FIG. 2 can be formed to be adjacent to each other and directly connected to each other, and so are the n.sup.+ -type diffusion layer region 922 and the p.sup.+ -type diffusion layer region 933 in FIG. 2. In addition, the n.sup.+ -type diffusion layer regions 911 and 921 and the p.sup.+ -type diffusion layer region 931 can be arranged at minimum intervals that allow electrical isolation.
The CMOS SRAM cell as reference 2 will be described in detail below with reference to FIGS. 4 and 5. FIGS. 4 and 5 are plan views showing a single-port CMOS SRAM cell circuit implemented on an SOI substrate. FIG. 4 shows how an element region 1210, gate interconnections 1221, 1222 and 1223, contact holes 1280a to 1280i, first aluminum interconnections 1271 and 1272, and second aluminum interconnections 1261 and 1262 are formed. FIG. 5 shows how the element region 1210 and the gate interconnections 1221, 1222, and 1223 are formed.
The gate interconnection 1221 in FIGS. 4 and 5 corresponds to the gates of the NMOS transistors 321 and 322 as the transfer gates in FIG. 6. The gate interconnection 1222 (1223) in FIGS. 4 and 5 corresponds to the gates of the PMOS transistor 301 (302) and the NMOS transistor 311 (312) in FIG. 6.
As shown in FIG. 4, the CMOS SRAM cell circuit as reference 2 is further characterized in that adjacent CMOS SRAM cells share the contact hole 1280a to which the power supply (Vdd) potential is applied, the contact holes 1280b and 1280c to which the ground (Gnd) potential is applied, and the contact holes 1280d and 2180e to which the potentials of signals supplied through the bit lines (the bit lines D and DB in FIG. 6) are applied.
In addition, the CMOS SRAM cell as reference 2 includes the following characteristic feature realized by the SOI CMOS technique. As shown in FIG. 5, the drain diffusion layer of an NMOS transistor (the transistor 311 or 312 in FIG. 6) of a flip-flop and the drain diffusion layer of an NMOS transistor (the transistor 321 or 322 in FIG. 6) as a transfer gate, or an n.sup.+ -type diffusion layer region 1213 (1216) as a source diffusion layer are arranged to be adjacent to a p.sup.+ -type diffusion layer region 1212 (1215) as the drain diffusion layer of a PMOS transistor of a flip-flop through a line 1231 (1232) as a boundary. As a result, three diffusion layer regions can be formed as a common diffusion layer with respect to each of the two lines 1231 and 1232, and hence the area of each SRAM cell can be reduced.
The CMOS SRAM cell as reference 2, however, has the following problem.
In the CMOS SRAM cell as reference 2 to which the SOI CMOS technique is applied, the distance between a p.sup.+ -type diffusion layer region and an n.sup.+ -type diffusion layer region and the area of a diffusion layer region constituting a part of the diffusion layer of a MOS transistor of the SRAM cell can be reduced as compared with the SRAM cell as reference 1 to which the bulk CMOS technique is applied. However, the area of each SRAM cell is substantially determined by the contact holes and the aluminum interconnections which are required to connect the nodes of each memory cell and the areas of the diffusion layers of the MOS transistors of each SRAM cell. It is therefore difficult to further reduce the area disclosed in reference 2.